Technical Field
The present disclosure relates generally to high frequency signal generation circuits, and more specifically to high frequency signal generation circuits utilizing a passive mixer circuit to generate a high frequency local oscillator signal.
Description of the Related Art
Most all electronic devices include various wired and wireless communications interfaces for communicating among components within the device and with external devices and networks. A typical laptop computer, for example, will include one or more Universal Serial Bus (USB) communication ports as well as Peripheral Connect Interface (PCI) Express (PCIe) communications ports for communication with video cards, storage devices, and other components of the laptop. Current versions of these USB and PCIe communications protocols utilize very high frequency Gigahertz (GHz) clock signals in operation. A common approach for generating the required clock signal utilizes a voltage controlled oscillator (VCO) in combination with a frequency doubling circuit for doubling the frequency of a signal from VCO to generate the required GHz clock signal. For the PCIe 4.0 standard operating at 16 Gb/s, for example, a standalone 8 GHz VCO could be utilized or a 4 GHz VCO in combination with a frequency doubling circuit utilized to generate an 8 GHz clock signal.
To lower power consumption and improve phase noise at 1 MHz, as well as to increase a tuning range for the clock signal, a 4 GHz to 6 GHz VCO is generally considered to be a good choice for generating a clock signal to cover all the standards. Where the amplitude of the signal generated by the VCO has a relatively high amplitude, as required in some applications, harmonics on the signal generated by the VCO can have sufficient magnitudes to increase the deterministic jitter caused by duty cycle error of the clock signal generated by the frequency doubling circuit. Jitter is the deviation from true periodicity of a periodic signal, and deterministic jitter is jitter that is not random but is predictable and reproducible. Deterministic jitter is proportional to the level of spurious power caused by such duty cycle errors and must be below specified threshold levels in these communication standards. There is a need for improved approaches for generating high frequency clock signals with deterministic jitter below specified threshold levels.